/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved.
 * Description: RDMA common context related macros.
 * Create: 2021-12-30
 */

#ifndef ROCE_CTX_API_H
#define ROCE_CTX_API_H

#include "roce_compile_macro.h"
#include "roce_wqe_format.h"
#include "roce_xqe_format.h"
#include "rdma_context_format.h"


enum ROCE_TIMER_ID_E {
    ROCE_TIMER_ID_ACK = 0,
    ROCE_TIMER_ID_DCQCN_RCNP,
    ROCE_TIMER_ID_WND_LESS_THAN_MTU,
    ROCE_TIMER_ID_MAX = 4,
    ROCE_TIMER_ID_QP_DEL = 7
};

enum roce_qpc_ulp_type {
    ROCE_ULP_STD = 0,
    ROCE_ULP_PLOG,
    ROCE_ULP_VBS,
    ROCE_ULP_OSD,
    ROCE_ULP_NOFAA
};

enum roce_req_rsp_side {
    ROCE_REQ_SIDE = 0,
    ROCE_RSP_SIDE
};

enum roce_rq_cqe_mask {
    ROCE_CQEMASK_WRITE = 0,
    ROCE_CQEMASK_SEND
};

enum ROCE_FLOWID_E {
    ROCE_FLOWID_0 = 0,
    ROCE_FLOWID_1,
    ROCE_FLOWID_2
};

enum ROCE_STGID_E {
    ROCE_STGID_0 = 0,
    ROCE_STGID_1,
    ROCE_STGID_2,
    ROCE_STGID_3,
    ROCE_STGID_4,
    ROCE_STGID_5,
    ROCE_STGID_6,
    ROCE_STGID_7
};

enum ROCE_EVENT_STG_E {
    ROCE_EVENT_STG_SQ = 0,
    ROCE_EVENT_STG_SQA,
    ROCE_EVENT_STG_RQ,
    ROCE_EVENT_STG_RQA,
    ROCE_EVENT_STG_SQA_2HOST,
    ROCE_EVENT_STG_DCC,
    ROCE_EVENT_STG_VERBS,
    ROCE_EVENT_STG_NO
};

#define ROCE_SQ_STGID ROCE_STGID_0
#define ROCE_RQ_STGID ROCE_STGID_1
#define ROCE_VERBS_STGID ROCE_STGID_2
#define ROCE_DCC_STGID ROCE_STGID_3
#define ROCE_RQ_ACK_STGID ROCE_STGID_4
#define ROCE_SQ_ACK_STGID ROCE_STGID_5
#define ROCE_SQA_2HOST_STGID ROCE_STGID_6
#define ROCE_REBIND_STGID QU_STG_ID_RSVD

/* *********TABLE SIZE******* */
#define WQEBB_SIZE_SHIFT 6 // 64b
#define ROCE_GET_WQBB_NUM_PERWQE(wqe_len_8b) (BYTE8_TO_BYTES(wqe_len_8b) >> WQEBB_SIZE_SHIFT)

#define ROCE_GID_TABLE_SIZE (32)
#define ROCE_MPT_TABLE_SIZE (64)
#define ROCE_MTT_TABLE_SIZE (8)
#define ROCE_CQC_TABLE_SIZE (128)
#define ROCE_SRQC_TABLE_SIZE (64)
#define ROCE_RDMARC_TABLE_SIZE (32)
#define ROCE_QPC_TABLE_SIZE (512)
#define ROCE_WQE_MAX_SIZE (256)
#define ROCE_CM_MAD_MEG_LEN (64)

#define ROCE_MTT_QUERY_SIZE (16)
#define ROCE_PCNT_QUERY_SIZE (16)

#define ROCE_CQE_LEN (64)
#define ROCE_CQE_LEN_SHIFT (6)
#define ROCE_RESIZE_CQE_LEN (64)

#define ROCE_QPC_RRWC_SEG_SIZE (32)
#define ROCE_QPC_RCC_SEG_SIZE (32)
#define ROCE_QPC_SQPC_SEG_SIZE (64)
#define ROCE_QPC_SQC_SEG_SIZE (64)
#define ROCE_QPC_SQAC_SEG_SIZE (64)
#define ROCE_QPC_RQC_SEG_SIZE (64)
#define ROCE_QPC_QPCC_SEG_SIZE (32)
#define ROCE_QPC_HW_SEG_SIZE (ROCE_QPC_RRWC_SEG_SIZE + ROCE_QPC_RCC_SEG_SIZE + ROCE_QPC_SQC_SEG_SIZE + \
    ROCE_QPC_SQAC_SEG_SIZE + ROCE_QPC_RQC_SEG_SIZE + ROCE_QPC_QPCC_SEG_SIZE)
#define ROCE_QPC_TIMER_SEG_SIZE (32)
#define ROCE_QPC_SW_SEG_SIZE (192)
#define ROCE_QPC_SW_DCQCN_SIZE (16)
#define ROCE_QPC_SW_NOFAA_SIZE ROCE_QPC_QPCC_SEG_SIZE
#define ROCE_QPC_SW_SQC_SIZE (20)
#define ROCE_QPC_SW_SQAC_SIZE (36)
#define ROCE_QPC_SW_RQC_SIZE (20)
#define ROCE_QPC_SW_RQAC_SIZE (20)
#define ROCE_QPC_SW_STGID_SIZE (68)

#define ROCE_QPC_EXT_SW_SEG_SIZE (32)

#define ROCE_QPC_RRWC_DW_SIZE (8)
#define ROCE_QPC_RCC_DW_SIZE (8)
#define ROCE_QPC_SQPC_DW_SIZE (16)
#define ROCE_QPC_SQC_DW_SIZE (16)
#define ROCE_QPC_SQAC_DW_SIZE (16)
#define ROCE_QPC_RQC_DW_SIZE (16)
#define ROCE_QPC_QPCC_DW_SIZE (8)
#define ROCE_QPC_TIMER_DW_SIZE (8)
#define ROCE_QPC_SW_DW_SIZE (48)
#define ROCE_QPC_SW_DCQCN_DW_SIZE (8)
#define ROCE_QPC_SW_NOFAA_DW_SIZE ROCE_QPC_QPCC_DW_SIZE

#define ROCE_QPC_SW_SEG_DWORD_LEN (ROCE_QPC_SW_SEG_SIZE >> 2)
#define ROCE_QPC_HW_SEG_DWORD_LEN (ROCE_QPC_HW_SEG_SIZE >> 2)
#define ROCE_QPC_SW_DCQCN_DWORD_LEN (ROCE_QPC_SW_DCQCN_SIZE >> 2)
#define ROCE_QPC_SW_NOFAA_DWORD_LEN (ROCE_QPC_SW_NOFAA_SIZE >> 2)
#define ROCE_QPC_SW_STGID_DWORD_LEN (ROCE_QPC_SW_STGID_SIZE >> 2)
#define ROCE_QPC_DWORD_LEN (ROCE_QPC_TABLE_SIZE >> 2)
#define ROCE_MPT_DWORD_LEN (ROCE_MPT_TABLE_SIZE >> 2)
#define ROCE_CQC_DWORD_LEN (ROCE_CQC_TABLE_SIZE >> 2)
#define ROCE_SRQC_DWORD_LEN (ROCE_SRQC_TABLE_SIZE >> 2)
#define ROCE_GID_DWORD_LEN (ROCE_GID_TABLE_SIZE >> 2)
#define ROCE_CM_MAD_DWORD_LEN (ROCE_CM_MAD_MEG_LEN >> 2)

#define ROCE_RDMARC_MAX_DATA_DW_LEN (ROCE_RDMARC_TABLE_SIZE >> 2)

#define ROCE_SQ_WQE_SEND_TASK_SEG_LEN (16)
#define ROCE_SQ_WQE_UD_SEND_TASK_SEG_LEN (64)
#define ROCE_SQ_WQE_RDMA_TASK_SEG_LEN (32)
#define ROCE_SQ_WQE_ATOMIC_TASK_SEG_LEN (32)
#define ROCE_SQ_WQE_MASK_ATOMIC_CMPSWP_TASK_SEG_LEN (48)
#define ROCE_SQ_WQE_SEND_WRITE_COM_TASK_SEG_LEN (16)

/* ******************************************************** */
enum ROCE_QP_CTX_OFF_E {
    ROCE_CTX_RRWC_OFF = 0,
    ROCE_CTX_RCC_OFF = 32,
    ROCE_CTX_SQC_OFF = 64,
    ROCE_CTX_SQAC_OFF = 128,
    ROCE_CTX_RQC_OFF = 192,
    ROCE_CTX_QPCC_OFF = 256,
    ROCE_CTX_TIMER_OFF = 288,
    ROCE_CTX_SW_OFF = 320,
    ROCE_CTX_SW_SQC_OFF = 400,
    ROCE_CTX_SW_SQAC_OFF = 416,
    ROCE_CTX_SW_RQC_OFF = 448,
    ROCE_CTX_SW_RQAC_OFF = 464
};
#define ROCE_CTX_SQPC_OFF ROCE_CTX_RRWC_OFF

#define ROCE_MISC_RRWC_OFFSET_16B_ALIGN (ROCE_CTX_RRWC_OFF >> 4)
#define ROCE_MISC_RCC_OFFSET_16B_ALIGN (ROCE_CTX_RCC_OFF >> 4)
#define ROCE_MISC_SQC_OFFSET_16B_ALIGN (ROCE_CTX_SQC_OFF >> 4)
#define ROCE_MISC_SQAC_OFFSET_16B_ALIGN (ROCE_CTX_SQAC_OFF >> 4)
#define ROCE_MISC_RQC_OFFSET_16B_ALIGN (ROCE_CTX_RQC_OFF >> 4)
#define ROCE_MISC_QPCC_OFFSET_16B_ALIGN (ROCE_CTX_QPCC_OFF >> 4)
#define ROCE_MISC_TIMERC_OFFSET_16B_ALIGN (ROCE_CTX_TIMER_OFF >> 4)
#define ROCE_MISC_SW_OFFSET_16B_ALIGN (ROCE_CTX_SW_OFF >> 4)
#define ROCE_MISC_SW_OFFSET64_16B_ALIGN ((ROCE_CTX_SW_OFF + 64) >> 4)
#define ROCE_MISC_SW_OFFSET128_16B_ALIGN ((ROCE_CTX_SW_OFF + 128) >> 4)
#define ROCE_MISC_SQPC_OFFSET_16B_ALIGN (ROCE_CTX_SQPC_OFF >> 4)

#ifdef NOF_ROCE_AA_MODE_EN
#define ROCE_WB_CTX_SIZE    QU_WB_CTX_SIZE_224
#else
#define ROCE_WB_CTX_SIZE    QU_WB_CTX_SIZE_192
#endif

#define ROCE_RDMARC_ATOMIC_DATA_LEN (8)

#define ROCE_RDMARC_ATOMIC_DATA_DW_LEN (16 >> 2)
#define ROCE_RDMARC_ATOMIC_STATUS_DW_LEN (4 >> 2)
#define ROCE_RDMARC_ATOMIC_DATA_DW_OFF (16 >> 2)
#define ROCE_RDMARC_ATOMIC_STATUS_DW_OFF (28 >> 2)
/* ************************************************* */
#define ROCE_QPCC_RXE_DW_OFF (4)
#define ROCE_QPCC_RXE_DW_BITMASK (0X01C00000)
#define ROCE_RCC_RXE_DW_OFF (7)
#define ROCE_RRWC_RXE_DW_OFF (7)
#define ROCE_RCC_RAE_DW_BITMASK (~0X08000000)
#define ROCE_RCC_RRE_DW_BITMASK (~0X04000000)
#define ROCE_RRWC_RWE_DW_BITMASK (~0X08000000)

#define ROCE_QP_QPCC_GPAH_DW_OFF (6)
#define ROCE_QP_QPCC_GPAH_DW_BITMASK (~0X00FFFFFF)
#define ROCE_QP_QPCC_GPAL_DW_BITMASK (~0XFFFFFFFF)

#define ROCE_QP_RCC_RCPI_DW_OFF (5)
#define ROCE_QP_RCC_RCPI_DW_BITMASK (~0X000000FF)
#define ROCE_QP_RCC_RCCI_DW_BITMASK (~0X000000FF)

#define ROCE_QP_COM_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_QP_RCC_STATE_DW_OFF (7)
#define ROCE_QP_RCC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_QP_SQC_STATE_DW_OFF (2)
#define ROCE_QP_SQC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_QP_SQAC_STATE_DW_OFF (2)
#define ROCE_QP_SQAC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_QP_SQAC_WQEIDX_DW_OFF (2)
#define ROCE_QP_SQAC_WQEIDX_DW_BITMASK (~0X0000ffff)

#define ROCE_QP_RQC_STATE_DW_OFF (2)
#define ROCE_QP_RQC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_QP_RRWC_STATE_DW_OFF (7)
#define ROCE_QP_RRWC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_QP_RQC_SGEVLD_DW_OFF (0)
#define ROCE_QP_RQC_SGEVLD_DW_BITMASK (~0X80000000)

#define ROCE_MPT_STATE_DW_OFF (2)
#define ROCE_MPT_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_MPT_MWCNT_DW_OFF (10)
#define ROCE_MPT_MWCNT_DW_BITMASK (~0Xffffffff)

#define ROCE_SRQC_STATE_DW_OFF (2)
#define ROCE_SRQC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_CQC_STATE_DW_OFF (2)
#define ROCE_CQC_STATE_DW_BITMASK (~0Xf0000000)

#define ROCE_CQC_TIMEOUT_DW7_OFF (7)
#define ROCE_CQC_TIMEOUT_DW7_BITMASK (~0Xffffffff)

#define ROCE_CQC_TMR_TWID_DW10_OFF (10)
#define ROCE_CQC_TMR_TWID_DW_BITMASK (~0Xffff0000)

#define ROCE_SRQC_ERR_STATE (0x10000000)
#define ROCE_QPC_RQ_COMM_EST_OFF (27) /* *keep the same with qpc rq DW22 */

#define ROCE_RRWC_SGE_VLD (0x80000000)

#define ROCE_SQC_RST_STATE (0x0)
#define ROCE_SQAC_RST_STATE (0x0)
#define ROCE_RQC_RST_STATE (0x0)
#define ROCE_RCC_RST_STATE (0x0)
#define ROCE_RRWC_RST_STATE (0x0)

#define ROCE_QPC_DELED_STATE (0xCE)
#define ROCE_RC_KICKOFF_VALUE (0x5a5acece)

#define ROCE_CQC_MID_STATE_VALUE (0xe)
#define ROCE_CQC_MID_STATE (0xe0000000)

enum ROCE_SQPC_STATE_E {
    ROCE_SQPC_STATE_SW = 0,
    ROCE_SQPC_STATE_ERR = 1,
    ROCE_SQPC_STATE_HW = 0xF
};

enum ROCE_SRQC_STATE_E {
    ROCE_SRQC_STATE_SW = 0,
    ROCE_SRQC_STATE_ERR = 1,
    ROCE_SRQC_STATE_HW = 0xF
};

enum ROCE_CQC_STATE_E {
    ROCE_CQC_STATE_SW = 0,
    ROCE_CQC_STATE_ERR = 1,
    ROCE_CQC_STATE_OVERFLOW = 2,
    ROCE_CQC_STATE_HW = 0xF
};

enum ROCE_MPT_STATE_E {
    ROCE_MPT_STATE_VALID = 1,
    ROCE_MPT_STATE_FREE = 3,
    ROCE_MPT_STATE_ABORT = 4,
    ROCE_MPT_STATE_INVALID = 0xF
};

enum ROCE_MPT_R_W_E {
    ROCE_MPT_MW = 0,
    ROCE_MPT_MR
};

enum ROCE_MPT_BQP_E {
    ROCE_MPT_BQP_TYPE1 = 0,
    ROCE_MPT_BQP_TYPE2B
};

enum ROCE_MPT_DIF_MODE_E {
    ROCE_MPT_DIF_MODE_INS = 0,
    ROCE_MPT_DIF_MODE_DEL,
    ROCE_MPT_DIF_MODE_FWD
};

enum ROCE_MPT_SECTOR_SIZE_E {
    ROCE_MPT_SECTOR_SIZE_512 = 0,
    ROCE_MPT_SECTOR_SIZE_4KB
};

enum ROCE_MPT_METEDATA_SIZE_E {
    ROCE_MPT_METEDATA_SIZE_8 = 0,
    ROCE_MPT_METEDATA_SIZE_64
};


enum ROCE_MPT_SGL_MODE_E {
    ROCE_MPT_SGL_MODE_SINGLE = 0,
    ROCE_MPT_SGL_MODE_DOUBLE
};

enum ROCE_QPC_STATE_E {
    ROCE_QPC_STATE_RST = 0,
    ROCE_QPC_STATE_INIT,
    ROCE_QPC_STATE_RTR,
    ROCE_QPC_STATE_RTS,
    ROCE_QPC_STATE_SQD,
    ROCE_QPC_STATE_SQEr,
    ROCE_QPC_STATE_ERR,
    ROCE_QPC_STATE_DRAINING,
    ROCE_QPC_STATE_RSV
};


enum ROCE_MTT_LAYER_NUM_E {
    ROCE_MTT_LAYER_NUM_0 = 0,
    ROCE_MTT_LAYER_NUM_1,
    ROCE_MTT_LAYER_NUM_2,
    ROCE_MTT_LAYER_NUM_3,
    ROCE_MTT_LAYER_NUM_RSVD
};

enum ROCE_CQE_TYPE_E {
    /* *1-Send Completion; 0-Receive Completion */
    ROCE_RQ_CQE = 0,
    ROCE_SQ_CQE
};

enum ROCE_CQE_SIZE_E {
    ROCE_CQE_SIZE_0 = 0, /* * 4B */
    ROCE_CQE_SIZE_1 = 1, /* * 8B */
    ROCE_CQE_SIZE_2 = 2, /* * 16B */
    ROCE_CQE_SIZE_3 = 3  /* * 32B, RoCE fix 3 */
};

enum ROCE_CQE_RQ_OPTYPE_E {
    ROCE_CQE_RQ_OPTYPE_WRITE_IMMEDIATE = 0,
    ROCE_CQE_RQ_OPTYPE_SEND,
    ROCE_CQE_RQ_OPTYPE_SEND_IMMEDIATE,
    ROCE_CQE_RQ_OPTYPE_SEND_INVALIDATE,
    ROCE_CQE_RQ_OPTYPE_WRITE,
    ROCE_CQE_RQ_OPTYPE_READ
};

enum ROCE_CQE_COMMON_OPTYPE_E {
    ROCE_CQE_COMMON_OPTYPE_RESIZE = 0x16,
    ROCE_CQE_COMMON_OPTYPE_ERR = 0x1e
};

enum ROCE_QPC_MTU_E {
    ROCE_PMTU_256B = 1,
    ROCE_PMTU_512B = 2,
    ROCE_PMTU_1KB = 3,
    ROCE_PMTU_2KB = 4,
    ROCE_PMTU_4KB = 5
};

enum {
    ROCE_DB_MTU_256B_SHIFT = 0,
    ROCE_DB_MTU_512B_SHIFT = 1,
    ROCE_DB_MTU_1K_SHIFT = 2,
    ROCE_DB_MTU_2K_SHIFT = 3,
    ROCE_DB_MTU_4K_SHIFT = 4,
};

enum ROCE_FLOW_ID_E {
    ROCE_STL_TIMER_FLOW = 0,
    ROCE_PKT_FLOW = 1,
    ROCE_DB_FLOW = 2,
    ROCE_TIMER_FLOW = 3,
    ROCE_ARM_FLOW = 4,
    ROCE_CMDQ_FLOW = 5,
    ROCE_NRET_FLOW = 6,
    ROCE_STL2STF_FLOW = 7,
};

enum {
    ROCE_IPSUTX_CHANNEL_5 = 0x0,  // ro
    ROCE_IPSUTX_CHANNEL_10 = 0x1, // rw
    ROCE_IPSUTX_CHANNEL_15 = 0x2, // rw
    ROCE_IPSUTX_CHANNEL_20 = 0x3  // wo
};

enum ROCE_SERVICE_TYPE_E {
    ROCE_RC_TYPE = 0,
    ROCE_UC_TYPE,
    ROCE_RD_TYPE,
    ROCE_UD_TYPE,
    ROCE_RSVD_TYPE,
    ROCE_XRC_5_TYPE = 0x5,
    ROCE_XRC_TYPE = 0x6,
    ROCE_XRC_6_TYPE = 0x6
};

enum ROCE_RC_FLAG_E {
    ROCE_UC_UD = 0,
    ROCE_RC_XRC
};

#define ROCE_MKEY_MPT_IDX_OFF (8)
#define ROCE_MKEY_GET_MPT_IDX(mkey) ((mkey) >> ROCE_MKEY_MPT_IDX_OFF)
/* ******************************************************** */
#define ROCE_ULP_TYPE_PLOG(qpc)  (u8)((qpc)->ucode_seg.common.dw0.bs.ulp_type == ROCE_ULP_PLOG)
#define ROCE_ULP_TYPE_VBS(qpc)  (u8)((qpc)->ucode_seg.common.dw0.bs.ulp_type == ROCE_ULP_VBS)
#define VERBS_ULP_TYPE_VBS(ulp_type)  (u8)((ulp_type) == ROCE_ULP_VBS)

#define ROCE_VLAN 1

#endif /* ROCE_CTX_API_H */
